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Freescale Semiconductor Data Sheet: Technical Data
An Energy Efficient Solution by Freescale
Document Number: MC9S08QB8 Rev. 3, 3/2009
MC9S08QB8
MC9S08QB8 Series
Covers: MC9S08QB8 and MC9S08QB4
Features * 8-Bit HCS08 Central Processor Unit (CPU) - Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature range of -40 C to 85 C - HC08 instruction set with added BGND instruction - Support for up to 32 interrupt/reset sources * On-Chip Memory - Up to 8 KB flash memory read/program/erase over full operating voltage and temperature - Up to 512 bytes random-access memory (RAM) - Security circuitry to prevent unauthorized access to RAM and flash contents * Power-Saving Modes - Two very low power stop modes - Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents - Low power run - Low power wait - 6 s typical wakeup time from stop3 mode - Typical stop current of 250 nA at 3 V, 25 C * Clock Source Options - Oscillator (XOSC) -- Very low-power, loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz - Internal Clock Source (ICS) -- Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1 MHz to 10 MHz * System Protection - Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock - Low-voltage detection with reset or interrupt; selectable trip points - Illegal opcode detection with reset - Illegal address detection with reset - Flash block protection
28 SOIC Case 751F 16-Pin TSSOP Case 948F
TBD
24 QFN Case 1982-01
* Development Support - Single-wire background debug interface - Breakpoint capability to allow single breakpoint setting during in-circuit debugging * Peripherals - ADC -- 8-channel, 12-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V. - ACMP -- Analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; output can be tied internally to TPM input capture; operation in stop3 - TPM -- One 1-channel timer/pulse-width modulator (TPM) module; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; ACMP output can be tied internally to input capture - MTIM -- 8-bit modulo timer module with optional prescaler - RTC -- (Real-time counter) 8-bit modulo counter with binary or decimal based prescaler; external clock source for precise time base, time-of-day, calendar or task scheduling functions; free running on-chip low power oscillator (1 kHz) for cyclic wakeup without external components; runs in all MCU modes - SCI -- Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge - KBI -- 8-pin keyboard interrupt with selectable edge and level detection modes * Input/Output - 22 GPIOs and one input-only and one output-only pin. - Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins except PTA5. * Package Options - 28-pin SOIC, 24-pin QFN, 16-pin TSSOP
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2008-2009. All rights reserved.
Table of Contents
1 2 3 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 7 3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 7 3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . 8 3.5 ESD Protection and Latch-Up Immunity . . . . . . . 9 3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 10 3.7 Supply Current Characteristics . . . . . . . . . . . . . 13 3.8 External Oscillator (XOSC) Characteristics . . . . 15 3.9 Internal Clock Source (ICS) Characteristics . . . 16 3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 18 3.10.1Control Timing . . . . . . . . . . . . . . . . . . . . . 18 3.10.2TPM Module Timing . . . . . . . . . . . . . . . . 19 3.11 Analog Comparator (ACMP) Electricals . . . . . . .20 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .20 3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .23 3.14 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .24 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .25 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . .25
4 5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev 1 2 3 Date 10/22/2008 12/17/2008 3/6/2009 Initial public released. Completed all the TBDs in Table 8. Corrected the 24-pin QFN package information. Changed VDDAD and VSSAD to VDDA and VSSA separatedly. In Table 7, updated the |IIn|, |IOZ| and added |IOZTOT|. In Table 11, updated the DCO output frequency range-trimmed, and updated some of the symbols. Description of Changes
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08QB8RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
MC9S08QB8 Series MCU Data Sheet, Rev. 3 2 Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
PTA7 PTA6 PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTA3/KBIP3/ADP3 PTA2/KBIP2/ADP2 PTA1/KBIP1/ADP1/ACMP- PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTB7/EXTAL PTB6/XTAL PTB5/TPMCH0 PORT B PTB4 PTB3/KBIP7/ADP7 PTB2/KBIP6/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 PTC7 PTC6 PTC5 PORT C 20 MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSC) VSS VDD VOLTAGE REGULATOR KEYBOARD INTERRUPT (KBI) PTC4 PTC3 PTC2 PTC1 PTC0
The block diagram shows the structure of the MC9S08QB8 MCU.
HCS08 CORE CPU BDC ANALOG COMPARATOR (ACMP) 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 8-BIT MODULO TIMER MODULE (MTIM) REAL-TIME COUNTER (RTC) PORT A VREFL/VSSA VREFH/VDDA
HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP IRQ LVD
USER FLASH (MC9S08QB8 = 8192 BYTES) (MC9S08QB4 = 4096 BYTES) USER RAM (MC9S08QB8 = 512 BYTES) (MC9S08QB4 = 256 BYTES)
16-BIT TIMER/PWM MODULE (TPM)
SERIAL COMMUNICATIONS INTERFACE MODULE (SCI)
pins not available on 24-pin or 16-pin packages pins not available on 16-pin package
1
VDDA/VREFH and VSSA/VREFL are double bonded to VDD and VSS respectively in16-pin package.
Figure 1. MC9S08QB8 Series Block Diagram
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 3
Pin Assignments
2
Pin Assignments
Table 1. Pin Availability by Package Pin-Count
Pin Number 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
1
This chapter shows the pin assignments for the MC9S08QB8 series devices.
<-- Lowest Port Pin PTC5 PTC4 PTA5 PTA4 IRQ ACMPO TCLK BKGD RESET MS VDD VDDA/VREFH VSSA/VREFL VSS PTB7 PTB6 PTB5 PTB4 PTC3 PTC2 PTC1 PTC0 PTB3 PTB2 PTB1 PTB0 PTA7 PTA6 PTA3 PTA2 PTA1 PTA0 PTC7 PTC6 KBIP3 KBIP2 KBIP1 KBIP0 TPMCH0 ADP3 ADP2 ADP12 ADP02 ACMP-2 ACMP+2 KBIP7 KBIP6 KBIP5 KBIP4 TxD RxD ADP7 ADP6 ADP5 ADP4 TPMCH0
1
Priority Alt 2
--> Highest Alt 3 Alt 4
24 -- -- 23 24 1 2 3 4 5 6 7 8 -- -- 9 10 11 12 13 14 15 16 17 18 19 20 21 22
16 -- -- 1 2 3 -- -- 4 5 6 7 8 -- -- -- -- 9 10 11 12 -- -- 13 14 15 16 -- --
Alt 1
EXTAL XTAL
TPMCH0 pin can be repositioned using at PTB5 TPMCH0PS in SOPT2, default reset location is PTA0. 2 If ADC and ACMP are enabled, both modules will have access to the pin.
MC9S08QB8 Series MCU Data Sheet, Rev. 3 4 Freescale Semiconductor
Pin Assignments
PTC5 PTC4 PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS VDD VDDA/VREFH VSSA/VREFL VSS PTB7/EXTAL PTB6/XTAL PTB5/TPMCH0 PTB4 PTC3 PTC2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PTC6 PTC7 PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA1/KBIP1/ADP1/ACMP- PTA2/KBIP2/ADP2 PTA3/KBIP3/ADP3 PTA6 PTA7 PTB0/KBIP4/RxD/ADP4 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/ADP6 PTB3/KBIP7/ADP7 PTC0 PTC1
Pins shown in bold type are lost in the next lower pin count package.
Figure 2. MC9S08QB8 Series in 28-Pin SOIC Package
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 5
Pin Assignments
PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 20
PTA5/IRQ/TCLK/RESET
24 VDD 1 VDDA/VREFH 2 VSSA/VREFL 3 VSS 4 PTB7/EXTAL 5 PTB6/XTAL 6 7 PTB5/TPMCH0
23
22
PTC6
21
PTC7
19 18 PTA2/KBIP2/ADP2 17 PTA3/KBIP3/ADP3 16 PTA6 15 PTA7 14 PTB0/KBIP4/RxD/ADP4 13 PTB1/KBIP5/TxD/ADP5
8 PTB4
9
PTC1
10 PTC0
11 PTB3/KBIP7/ADP7
12 PTB2/KBIP6/ADP6 16 15 14 13 12 11 10 9
Pins shown in bold type are lost in the next lower pin count package.
Figure 3. MC9S08QB8 Series in 24-Pin QFN Packages
PTA1/KBIP1/ADP1/ACMP-
PTA4/ACMPO/BKGD/MS
PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS VDD VSS PTB7/EXTAL PTB6/XTAL PTB5/TPMCH0 PTB4
1 2 3 4 5 6 7 8
PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA1/KBIP1/ADP1/ACMP- PTA2/KBIP2/ADP2 PTA3/KBIP3/ADP3 PTB0/KBIP4/RxD/ADP4 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/ADP6 PTB3/KBIP7/ADP7
Figure 4. MC9S08QB8 Series in 16-Pin TSSOP Package
MC9S08QB8 Series MCU Data Sheet, Rev. 3 6 Freescale Semiconductor
Electrical Characteristics
3
3.1
Electrical Characteristics
Introduction
This chapter contains electrical and timing specifications for the MC9S08QB8 series of microcontrollers available at the time of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications P C
Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
T D
NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 7
Electrical Characteristics
Table 3. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range
1
Symbol VDD IDD VIn ID Tstg
Value -0.3 to 3.8 120 -0.3 to VDD + 0.3 25 -55 to 150
Unit V mA V mA C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 4. Thermal Characteristics
Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance 28-pin SOIC Thermal resistance 24-pin QFN Thermal resistance 16-pin TSSOP JA Symbol TA TJM Value TL to TH -40 to 85 95 70 92 129 Unit C C C/W C/W C/W
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD x JA) Eqn. 1
where:
MC9S08QB8 Series MCU Data Sheet, Rev. 3 8 Freescale Semiconductor
Electrical Characteristics
TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is:
PD = K / (TJ + 273C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD x (TA + 273C) + JA x (PD)2 Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification.
Table 5. ESD and Latch-up Test Conditions Model
Human Body
Description
Series resistance Storage capacitance Number of pulses per pin Series resistance
Symbol
R1 C -- R1 C --
Value
1500 100 3 0 200 3 -2.5 7.5
Unit
pF
pF
Machine
Storage capacitance Number of pulses per pin Minimum input voltage limit
V V
Latch-up Maximum input voltage limit
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 9
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics
No. 1 2 3
1
Rating1 Human body model (HBM) Charge device model (CDM) Latch-up current at TA = 85C
Symbol VHBM VCDM ILAT
Min 2000 500 100
Max -- -- --
Unit V V mA
Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted.
3.6
DC Characteristics
Table 7. DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Num C 1 Characteristic Symbol VDD All I/O pins, low-drive strength Output high voltage All I/O pins, high-drive strength VOH Condition -- VDD > 1.8 V, ILoad = -2 mA VDD > 2.7 V, ILoad = -10 mA VDD > 1.8V, ILoad = -2 mA IOHT VOUT < VDD VDD > 1.8 V, ILoad = 0.6 mA VOL VDD > 2.7 V, ILoad = 10 mA VDD > 1.8 V, ILoad = 3 mA IOLT VIH VIL Vhys |IIn| VOUT > VSS VDD > 2.7 V VDD > 1.8 V VDD > 2.7 V VDD > 1.8 V -- Min 1.8 VDD - 0.5 VDD - 0.5 VDD - 0.5 0 -- -- -- 0 0.70 x VDD 0.85 x VDD -- -- 0.06 x VDD -- Typical1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 3.6 -- -- -- -80 0.5 0.5 0.5 80 -- -- 0.35 x VDD 0.30 x VDD -- mV V mA V mA V Unit V
P Operating Voltage C
2
P C D C
3
Output high current
Max total IOH for all ports All I/O pins, low-drive strength
4
P C
Output low voltage
All I/O pins, high-drive strength
5
D
Output low current
Max total IOL for all ports all digital inputs all digital inputs all digital inputs all input only pins (Per pin)
6 7 8
P Input high C voltage P Input low C voltage C Input hysteresis
9
Input P leakage current Hi-Z (off-state) P leakage current
VIn = VDD or VSS
--
200
nA
10
all input/output (per pin)
|IOZ|
VIn = VDD or VSS
--
--
200
nA
MC9S08QB8 Series MCU Data Sheet, Rev. 3 10 Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C Total leakage combined C for all inputs and Hi-Z pins Pullup, P Pulldown resistors Pullup, C Pulldown resistors DC injection D current 3, 4,
5
Characteristic
Symbol
Condition
Min
Typical1
Max
Unit
10
All input only and I/O |IOZTOT|
VIn = VDD or VSS
--
--
2
A
11
all digital inputs except PTA5/IRQ/TCLK/RESET, when enabled PTA5/IRQ/TCLK/RESET, when enabled2 Single pin limit Total MCU limit, includes sum of all stressed pins
RPU, RPD RPU, RPD
--
17.5
--
52.5
k
12
--
17.5 -0.2
-- -- -- -- 0.6 1.4 -- 1.84 1.92 2.14 80 1.17
52.5 0.2 5 8 1.0 2.0 -- 1.88 1.96 2.26 -- 1.18
k mA mA pF V V s V V mV V
13 14 15 16 17 18 19 20 21
1 2 3 4 5
IIC CIn VRAM VPOR tPOR VLVD VLVW Vhys VBG
VIN < VSS, VIN > VDD -- -- -- -- VDD falling VDD rising VDD falling VDD rising -- --
-5 -- -- 0.9 10 1.80 1.88 2.08 -- 1.15
C Input Capacitance, all pins C RAM retention voltage C POR re-arm voltage D POR re-arm time P Low-voltage detection threshold P Low-voltage warning threshold C Low-voltage inhibit reset/recover hysteresis
6
P Bandgap Voltage Reference7
6 7
Typical values are measured at 25 C. Characterized, not tested The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear lower when measured externally on the pin. All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed. Factory trimmed at VDD = 3.0 V, Temp = 25 C
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 11
Electrical Characteristics
40 PULL-UP RESISTOR (k) 35 30 25 20 PULLUP RESISTOR TYPICALS PULLDOWN RESISTANCE (k)
85C 25C -40C
40 35 30 25 20
PULLDOWN RESISTOR TYPICALS
85C 25C -40C
1.8
2
2.2
2.4
2.6 2.8 VDD (V)
3
3.2
3.4
3.6
1.8
2.3
2.8 VDD (V)
3.3
3.6
Figure 5. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)
1.2 1 0.8 VOL (V) 0.6 0.4 0.2 0 0
TYPICAL VOL VS IOL AT VDD = 3.0 V
85C 25C -40C
0.2 0.15 VOL (V) 0.1 0.05 0
TYPICAL VOL VS VDD
85C, IOL = 2 mA 25C, IOL = 2 mA -40C, IOL = 2 mA
5
10 IOL (mA)
15
20
1
2
VDD (V)
3
4
Figure 6. Typical Low-Side Driver (Sink) Characteristics -- Low Drive (PTxDSn = 0)
TYPICAL VOL VS IOL AT VDD = 3.0 V
85C 25C -40C
1 0.8 0.6 VOL (V)
TYPICAL VOL VS VDD 0.4 0.3 VOL (V) 0.2 0.1 0 IOL = 3 mA 1 2 VDD (V) 3 4 IOL = 6 mA
85C 25C -40C
0.4 0.2 0 0 10 IOL (mA) 20 30
IOL = 10 mA
Figure 7. Typical Low-Side Driver (Sink) Characteristics -- High Drive (PTxDSn = 1)
MC9S08QB8 Series MCU Data Sheet, Rev. 3 12 Freescale Semiconductor
Electrical Characteristics
1.2 1 VDD - VOH (V) 0.8 0.6 0.4 0.2 0 0
TYPICAL VDD - VOH VS IOH AT VDD = 3.0 V
85C 25C -40C
0.25 0.2 VDD - VOH (V) 0.15 0.1 0.05 0
TYPICAL VDD - VOH VS VDD AT SPEC IOH
85C, IOH = 2 mA 25C, IOH = 2 mA -40C, IOH = 2 mA
-5
-10 IOH (mA))
-15
-20
1
2
VDD (V)
3
4
Figure 8. Typical High-Side (Source) Characteristics -- Low Drive (PTxDSn = 0)
0.4
0.8 TYPICAL VDD - VOH VS IOH AT VDD = 3.0 V
TYPICAL VDD - VOH VS VDD AT SPEC IOH
85C 25C -40C
VDD - VOH (V)
0.6 0.4 0.2 0 0
VDD - VOH (V)
85C 25C -40C
0.3 0.2 0.1 0 1
IOH = -10 mA IOH = -6 mA IOH = -3 mA 2 VDD (V) 3 4
-5
-10
-15 -20 IOH (mA)
-25
-30
Figure 9. Typical High-Side (Source) Characteristics -- High Drive (PTxDSn = 1)
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 13
Electrical Characteristics
Table 8. Supply Current Characteristics
Num 1 C P T T T T 3 T 4 5 6 T T T T P C 7 P C C C P C 8 P C C C
1
Parameter Run supply current FEI mode, all modules on Run supply current FEI mode, all modules off Run supply current LPRS=0, all modules off
Symbol RIDD RIDD
Bus Freq 10 MHz 1 MHz 10 MHz 1 MHz 16 kHz FBILP 16 kHz FBELP 16 kHz FBELP 10 MHz 1 MHz 16 kHz FBELP -- --
VDD (V) 3
Typical1 5.60 0.80 3.60
Max 6 -- -- -- --
Unit mA
Temp (C) -40 to 85C
2
3
0.75 165
mA
-40 to 85C
RIDD
3
105 7.3 570 290
A -- -- -- -- -- 0.65 0.8 2 0.5 0.6 1.6 0.80 1.8 5.8 0.6 1.5 5.0 A A A A A
-40 to 85C
Run supply current LPRS=1, all modules off Wait mode supply current FEI mode, all modules off Wait mode supply current LPRS = 1, all mods off
RIDD WIDD WIDD
3 3
-40 to 85C
-40 to 85C -40 to 85C -40 to 25C 70C 85C -40 to 25C 70C 85C -40 to 25C 70C 85C -40 to 25C 70C 85C
3
1 0.25
3
0.5 1 0.2
Stop2 mode supply current
S2IDD
-- -- -- -- -- -- 3 2
0.3 0.7 0.45 1 3 0.3
Stop3 mode supply current no clocks active
S3IDD
-- -- -- -- 2
0.8 2.5
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value.
Table 9. Stop Mode Adders
Temperature Num 1 2 3 C T T T Parameter LPO ERREFSTEN IREFSTEN1 -- RANGE = HGO = 0 -- Condition -40C 50 1000 63 25C 75 1000 70 70C 100 1100 77 85C 150 1500 81 nA nA A Units
MC9S08QB8 Series MCU Data Sheet, Rev. 3 14 Freescale Semiconductor
Electrical Characteristics
Table 9. Stop Mode Adders (continued)
Temperature Num 4 5 6 7
1
C T T T T
Parameter RTC LVD1 ACMP ADC1
1
Condition -40C Does not include clock source current LVDSE = 1 Not using the bandgap (BGBE = 0) ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) 50 90 18 95 25C 75 100 20 106 70C 100 110 22 114 85C 150 115 23 120
Units nA A A A
Not available in stop2 mode.
3.8
External Oscillator (XOSC) Characteristics
Table 10. XOSCVLP and ICS Specifications (Temperature Range = -40 to 85C Ambient)
Reference Figure 10 and Figure 11 for crystal or resonator circuits.
Typ1
Num
C
Characteristic
Symbol
Min
Max
Unit
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) Load capacitors Low range (RANGE=0), low power (HGO=0) D Other oscillator settings Feedback resistor Low range, low power (RANGE = 0, HGO = 0)2 D Low range, high gain (RANGE = 0, HGO = 1) High range (RANGE = 1, HGO = X) Series resistor -- Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz Crystal start-up time 4 Low range, low power Low range, high gain C High range, low power High range, high gain Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode D FBE or FBELP mode
t t
flo fhi fhi
32 1 1
-- -- --
38.4 16 8
kHz MHz MHz
2
C1,C2
See Note 2 See Note 3
3
RF
-- -- -- -- -- -- -- -- -- -- -- -- --
-- 10 1 -- 100 0 0 0 0 600 400 5 15
-- -- -- -- -- -- 0 10 20 -- -- -- --
M
4
RS
k
CSTL
5
ms
CSTH
6
fextal
0.03125 0
-- --
20 20
MHz
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 15
Electrical Characteristics Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0. 3 See crystal or resonator manufacturer's recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications.
1 2
XOSCVLP EXTAL XTAL RS
RF
C1
Crystal or Resonator C2
Figure 10. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP EXTAL XTAL
Crystal or Resonator
Figure 11. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Num 1 2 3 4 5 6 C P P T P P C
Internal Clock Source (ICS) Characteristics
Table 11. ICS Frequency Specifications (Temperature Range = -40 to 85C Ambient)
Characteristic Average internal reference frequency -- factory trimmed at VDD = 3.6 V and temperature = 25 C Internal reference frequency -- user trimmed Internal reference start-up time DCO output frequency range -- Low range (DRS = 00) trimmed2 DCO output frequency2 Reference = 32768 Hz and DMX32 = 1 Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Symbol fint_t fint_ut tIRST fdco_t fdco_DMX32 fdco_res_t Min. -- 31.25 -- 16 Typical1 32.768 -- 60 -- Max. -- 39.06 100 20 -- 0.2 Unit kHz kHz s MHz MHz %fdco
-- --
19.92 0.1
MC9S08QB8 Series MCU Data Sheet, Rev. 3 16 Freescale Semiconductor
Electrical Characteristics
Table 11. ICS Frequency Specifications (Temperature Range = -40 to 85C Ambient) (continued)
Num 7 C C Characteristic Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) Total deviation of DCO output from trimmed frequency3 Over full voltage and temperature range Over fixed voltage and temperature range of 0 to 70 C Symbol fdco_res_t fdco_t tAcquire CJitter Min. -- Typical1 0.2 Max. 0.4 Unit %fdco
8 10 11
1 2
C
-- -- --
-1.0 to 0.5 0.5 -- 0.02
2 1 1 0.2
%fdco ms %fdco
C FLL acquisition time4 C Long term jitter of DCO output clock (averaged over 2-ms interval)5
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This parameter is characterized and not tested on each device. 4 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 5 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
1.00%
0.50%
0.00% Deviation (%) -60 -40 -20 -0.50% 0 20 40 60 80 100 120
-1.00%
TBD
Temperature
-1.50%
-2.00%
Figure 12. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 17
Electrical Characteristics
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1
Control Timing
Table 12. Control Timing
Num 1 2 3 4 5 6
C D D D D D D
Rating Bus frequency (tcyc = 1/fBus) Internal low power oscillator period External reset pulse Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 Port rise and fall time -- Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) width2
Symbol fBus tLPO textrst trstdrv tMSSU tMSH
Min DC 700 100 34 x tcyc 500 100
Typical1 -- -- -- -- -- --
Max 10 1300 -- -- -- --
Unit MHz s ns ns ns s
7
D
tILIH, tIHIL
100 1.5 x tcyc 100 1.5 x tcyc
-- -- -- --
-- -- -- --
ns
8
D
tILIH, tIHIL
ns
tRise, tFall
-- --
16 23
-- --
ns
9
D
Port rise and fall time -- High output drive (PTxDS = 1) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) 10
1 2
tRise, tFall
-- -- --
5 9 4
-- -- --
ns
D
Voltage regulator recovery time
tVRR
s
Typical values are based on characterization data at VDD = 3.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t MSH after VDD rises above VLVD. 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range -40C to 85C.
textrst RESET PIN
Figure 13. Reset Timing
MC9S08QB8 Series MCU Data Sheet, Rev. 3 18 Freescale Semiconductor
Electrical Characteristics
tIHIL KBIPx
IRQ/KBIPx tILIH
Figure 14. IRQ/KBIPx Timing
3.10.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 13. TPM Input Timing
No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTEXT tTEXT tTCLKH tTCLKL fICPW Min DC 4 1.5 1.5 1.5 Max 1/4 fop -- -- -- -- Unit MHz tCYC tCYC tCYC tCYC
tCYC ipg_clk
tTEXT EXTERNAL CLOCK tTCLKH tTCLKL
tICPW
INPUT CAPTURE
Figure 15. Timer Input Capture Pulse
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 19
Electrical Characteristics
3.11
C D D D P C P C
Analog Comparator (ACMP) Electricals
Table 14. Analog Comparator Electrical Specifications
Characteristic Symbol VPWR IDDAC VAIN VAIO VH IALKG tAINIT Min 1.8 -- VSS - 0.3 -- 3.0 -- -- Typical -- 20 -- 20 9.0 -- -- Max 3.6 35 VDD 40 15.0 1.0 1.0 Unit V A V mV mV A s
Supply voltage Supply current (active) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay
3.12
ADC Characteristics
Table 15. 12-Bit ADC Operating Conditions
Conditions Absolute Symbol VDDA VDDA VSSA IDDAD VADIN CADIN RADIN 12 bit mode fADCK > 4MHz fADCK < 4MHz -- -- RAS fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) -- -- -- 0.4 fADCK 0.4 -- -- -- -- -- 5 10 10 8.0 MHz 4.0 -- -- 2 5 k External to MCU Min 1.8 -100 -100 -- VREFL -- -- Typical1 -- 0 0 0.007 -- 4.5 5 Max 3.6 100 100 0.8 VREFH 5.5 7 Unit V mV mV A V pF k Comment
Characteristic
Supply voltage
Delta to VDD (VDD - VDDA)2 Delta to VSS (VSS - VSSA)2 Stop, Reset, Module Off
Ground voltage Supply Current Input Voltage Input Capacitance Input Resistance
Analog Source Resistance
10 bit mode
ADC Conversion Clock Freq.
1
High Speed (ADLPC = 0) Low Power (ADLPC = 1)
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference.
MC9S08QB8 Series MCU Data Sheet, Rev. 3 20 Freescale Semiconductor
Electrical Characteristics
NOTE VDDA/VSSA pins do not exist in 16-pin package. The signals are derived internally by double bonding to VDD/VSS pair of pins.
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS + VADIN - Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
VAS
+ -
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 16. ADC Input Impedance Equivalency Diagram
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 21
Electrical Characteristics
Table 16. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)
Characteristic Supply Current ADLPC=1 ADLSMP=1 ADCO=1 Supply Current ADLPC=1 ADLSMP=0 ADCO=1 Supply Current ADLPC=0 ADLSMP=1 ADCO=1 Supply Current ADLPC=0 ADLSMP=0 ADCO=1 Supply Current ADC Asynchronous Clock Source Conversion Time (Including sample time) Stop, Reset, Module Off High Speed (ADLPC = 0) P Low Power (ADLPC = 1) Short Sample (ADLSMP = 0) T Long Sample (ADLSMP = 1) Short Sample (ADLSMP = 0) Sample Time Long Sample (ADLSMP = 1) 12-bit mode Total Unadjusted Error Total Unadjusted Error 10-bit mode 8-bit mode 10-bit mode 8-bit mode 12-bit mode Differential Non-Linearity 10-bit mode 8-bit mode T P T P T T P DNL ETUE ETUE T tADS -- -- -- -- -- -- -- -- -- 23.5 3.0 1 0.5 1.5 0.7 1.75 0.5 0.3 -- -- -- -- -- LSB2 -- -- -- -- LSB2 LSB2 For 28-pin and 24-pin packages only. Includes quantization For 16-pin package only. Includes quantization tADC -- -- 40 3.5 -- -- ADCK cycles fADACK Conditions C Symbol Min Typical1 Max Unit Comment
T
IDDAD
--
120
--
A
T
IDDAD
--
202
--
A
T
IDDAD
--
288
--
A
T
IDDAD
--
0.532
1
mA
T
IDDAD
-- 2 1.25 --
0.007 3.3 2 20
0.8 5
A MHz tADACK = 1/fADACK
3.3 -- ADCK cycles
See reference manual for conversion time variances
T
Monotonicity and No-Missing-Codes guaranteed
MC9S08QB8 Series MCU Data Sheet, Rev. 3 22 Freescale Semiconductor
Electrical Characteristics
Table 16. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Characteristic Conditions 12-bit mode Integral Non-Linearity 10-bit mode C 8-bit mode 12-bit mode Zero-Scale Error 10-bit mode 8-bit mode Zero-Scale Error 10-bit mode 8-bit mode 12-bit mode Full-Scale Error 10-bit mode 8-bit mode Full-Scale Error 10-bit mode 8-bit mode 12-bit mode Quantization Error 10-bit mode 8-bit mode 12-bit mode Input Leakage Error 10-bit mode 8-bit mode Temp Sensor Slope Temp Sensor Voltage
1
C T
Symbol
Min --
Typical1 1.5 0.5 0.3 1.5 0.5 0.5 1.5 0.5 1 0.5 0.5 1 0.5 -1 to 0 -- -- 1 0.2 0.1 1.646 1.769 701.2
Max -- -- -- -- 1.5 0.5 2.1 0.7 -- 1 0.5 1.5 0.5 -- 0.5 0.5 -- 4 1.2 --
Unit
Comment
INL
-- --
LSB2
C P EZS
-- -- -- -- EZS -- -- EFS -- -- -- EFS -- --
LSB
2
T
P T T P
For 28-pin and 24-pin packages only. VADIN = VSSA For 16-pin package only. VADIN = VSSA For 28-pin and 24-pin packages only. VADIN = VDDA For 16-pin package only. VADIN = VDDA
LSB2
LSB
2
T
T T
LSB2
D
EQ
-- -- --
LSB2
D
EIL
0 0 --
LSB2
Pad leakage3 * RAS
-40C- 25C D 25C- 85C 25C D VTEMP25 m
mV/C -- -- -- -- mV
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH - VREFL)/2N 3 Based on input pad leakage current. Refer to pad electricals.
3.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 23
Electrical Characteristics
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the memory section.
Table 17. Flash Characteristics
C D D D D D D D D D D C C
1 2
Characteristic Supply voltage for program/erase -40C to 85C Supply voltage for read operation Internal FCLK frequency
1
Symbol Vprog/erase VRead fFCLK tFcyc
(2)
Min 1.8 1.8 150 5
Typical
Max 3.6 3.6 200 6.67
Unit V V kHz s tFcyc tFcyc tFcyc tFcyc
Internal FCLK period (1/FCLK) Byte program time (random location) Byte program time (burst mode) Page erase time Mass erase
2 (2)
tprog tBurst tPage tMass RIDDBP RIDDPE -- tD_ret -- -- 10,000 15
9 4 4000 20,000 4 6 -- 100,000 100 -- -- -- -- --
time(2) current3 endurance4 current3
Byte program Page erase
mA mA cycles years
Program/erase TL to TH = -40C to + 85C T = 25 C Data retention5
The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures DD with VDD = 3.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
3.14
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
MC9S08QB8 Series MCU Data Sheet, Rev. 3 24 Freescale Semiconductor
Ordering Information
4
Ordering Information
This section contains ordering information for the device numbering system. Example of the device numbering system:
MC 9 S08 QB 8 Status (MC = Fully Qualified) Memory (9 = Flash-based) Core Family C XX
Package designator (see Table 18) Temperature range (C = -40 C to 85 C) Approximate flash size in KB
5
Package Information
Table 18. Package Descriptions
Pin Count 28 24 16 Package Type Small Outline Integrated Circuit Quad Flat Non-Leaded Thin Shrink Small Outline Package Abbreviation SOIC QFN TSSOP Designator WL GK TG Case No. 751F 1982-01 948F Document No. 98ASB42345B 98ARL10608D 98ASH70247A
5.1
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 18.
MC9S08QB8 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 25
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Document Number: MC9S08QB8 Rev. 3 3/2009

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